import chisel3._
import chisel3.util._


class BcdTable extends Module {
    val io = IO(new Bundle {
        val address = Input(UInt(8.W))
        val data = Output(UInt(8.W))
    })
    
    val dataReg = RegInit(0.U(8.W))    

    val table = Wire(Vec(100, UInt(8.W)))
   
    // 二进制转换为BCD
    for (i <- 0 until 100) {
        table(i) := (((i/10)<<4) + i%10).U
    }

    dataReg :=  table(io.address)
    
    io.data := dataReg
}


/**
 * An object extending App to generate the Verilog code.
 */
object BcdTable extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new BcdTable())
}





